1. Field of the Invention
The present invention relates to an information processing apparatus which includes a plurality of arithmetic elements and is capable of dynamic reconfiguration.
2. Description of the Related Art
Miniaturization of elements thanks to the progress of semiconductor manufacturing techniques has made it possible to integrate an enormous number of transistors on a large scale integration (LSI). However, the miniaturization and an increase in the number of transistors increase static power (explained below). Further, power in operation increases as the processor frequency increases. As a result, performance and reduction of power consumption have a tradeoff relationship, and improvement of performance is approaching its limit.
As a means for further improving performance, an array arithmetic apparatus is receiving attention, in which a plurality of processor elements (PEs) such as a central processing unit (CPU), digital signal processor (DSP), single arithmetic device, and arithmetic unit are mounted on an LSI. The array arithmetic apparatus performs parallel processes by using a plurality of PEs, and can obtain high arithmetic performance even in a situation in which an increase in operating frequency by miniaturization in a process cannot be expected, compared to before.
In the future, logic performance can be improved by increasing the number of PEs to be mounted by the advance of large-scale techniques and integration techniques. However, performance improvement and power reduction cannot both be achieved unless a means or measure is taken to suppress power consumption which increases at the same time.
A measure to reduce dynamic power consumed by functional operation and static power generated just by supplying power to a transistor will be explained.
Dynamic power is power consumed by a current flowing to charge/discharge a parasitic capacitance upon a signal change, and a current flowing in transistor switching, such as a flow-through current. Hence, the dynamic power drawn can be reduced by suppressing signal changes as long as the functional operation is not hindered. A typical power saving method based on this principle is clock gating, which is widely used in general.
To the contrary, static power is power which is consumed for charges to be supplied to the parasitic capacitance of a transistor, and leakage current. Along with miniaturization in a process, the parasitic capacitance tends to decrease, and the leakage current tends to increase. In particular, as a polysilicon gate oxide film became thinner, the leakage current once exhibited an exponential increase. To reduce the leakage current, it is effective to restrict the voltage supplied to a transistor to be low, or shut down the transistor. Therefore, as a technique for reducing leakage power, power shutdown of blocks driven by the same power supply has been adopted popularly.
Power shutdown in a semiconductor integrated circuit is a technique of connecting a power supply path extending to a power shutdown target portion, with a power supply, by using a power supply switch formed from a transistor, and if necessary, switching the power supply switch between conduction and shutdown in the semiconductor integrated circuit. At present, the leakage current does not exhibit the conventional exponential increase thanks to improvements in materials and manufacturing methods, but still does increase linearly. Power shutdown will be important as a power reduction method. In the following description, a portion on an integrated circuit where supply and shutdown of power to an element arranged in a desired area can be controlled will be defined as a “power-supply controlled area”.
Even a large-scale array arithmetic apparatus uses the power shutdown technique to effectively reduce the leakage current. Power consumption can be suppressed by configuring a plurality of power-supply controlled areas and performing fine power management to partially shut down power to inactive PEs.
Under these circumstances, a method of reducing power consumption in an array arithmetic apparatus capable of dynamic reconfiguration has been examined. For example, there is proposed a method of changing switching of power-on/off and the wiring state between logical blocks based on preset power saving operation data. The power saving operation data is generated based on information about a power consumption profile, the transition time from the power saving state to the normal operation state, and the analysis result of a transition factor.
When processes are sequentially executed by a configuration using a processor capable of dynamic reconfiguration, mapping of circuit configuration information needs to be switched before executing the next process. There has been proposed a method of acquiring a free resource of an arithmetic device array or processor array mounted on a dynamic reconfiguration circuit, and mapping a process to the free resource.
However, since more advanced functions and higher performance will be required, it is predicted that integration using a leading-edge manufacturing process will be advanced to mount a large number of PEs. To reduce the leakage current effectively, it is necessary to configure a plurality of power-supply controlled areas and perform fine power management to partially shut down power to inactive PEs. However, as a larger number of power-supply controlled areas are arranged, the area of the power supply switch increases, and control of power shutdown and return becomes complicated.
When many PEs are mounted on a chip in the future, the area overhead of the power supply switch will cause a serious problem. Thus, one power-supply controlled area will be arranged for a plurality of PEs to configure power-supply controlled areas in various division forms.
If the number of power-supply controlled areas increases by N, there are 2N combinations of power shutdown and return. It is therefore difficult to grasp each arithmetic process state and circuit configuration state, and optimize power supply so that power is supplied only to the minimum set of PEs that need to be used.
When many PEs are mounted and power-supply controlled areas are configured in various division forms, it becomes more complex to, for example, control the power supply and circuit configuration in consideration of the configuration and physical arrangement of the power-supply controlled areas. Hence, it is necessary to search for an optimal configuration and perform control complying with the configuration.
To implement an advanced-function, high-performance array arithmetic apparatus, various complicated arithmetic processes need to be assigned to PEs more flexibly to improve the execution performance. It is predicted that there will be widely applied in the future a circuit capable of dynamic reconfiguration in which the circuit configuration is appropriately switched dynamically in accordance with a process to be executed, and a plurality of processes can be executed.
However, the conventional dynamic reconfiguration circuit does not perform mapping control of a process in consideration of power-supply controlled areas implemented in various division forms. The conventional method may disperse, to a plurality of power-supply controlled areas during the system operation, processes to be mapped to a processor array. For example, when a process is newly mapped to the processor array, it may be mapped to PEs that are currently in the power-off state even though it could be mapped to PEs already in the power-on state. In this case, a power-supply controlled area to which the process-mapped PE belongs needs to be changed to the power-on state, increasing the number of areas in the power-on state. As a result, static power is consumed by unwanted and unnecessary leakage current in the processor array.
Further, when a power-supply controlled area is changed to the power-on state, the parasitic capacitance in the power-supply controlled area needs to be charged, additionally consuming power by charging (to be referred to below as “charge power”). If such power-on/off switching of a power-supply controlled area occurs frequently, the charge power increases correspondingly, since the charge power that is drawn is in proportion to the switching count.
In this manner, in the conventional dynamic reconfiguration circuit, process mapping to the processor array does not consider the power-supply controlled area(s), so process mapping to reduce power consumption cannot be performed.